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hardware

7 posts
KERNEL

Interrupts: How Hardware Taps the Kernel on the Shoulder

A packet arrives, a key is pressed, a timer fires — and the CPU drops everything, mid-instruction-stream, to run kernel code. How interrupts work, why handlers are split in half, and how NAPI killed the interrupt storm.

SYSTEMS

SSD Internals: Why Your Disk Is a Small Computer That Lies

Flash can't overwrite in place, erases in giant blocks, and wears out per cell — so every SSD runs a translation layer that remaps, garbage-collects, and levels wear behind your back. Write amplification, TRIM, and the cliff at 90% full, explained.

FUNDAMENTALS

Two's Complement: Why -1 Is All Ones

Signed integers could have been encoded a dozen ways. Hardware settled on two's complement because it makes the adder ignorant of sign — one circuit for everything. The same choice explains INT_MIN, sign extension bugs, and why abs() can return a negative number.

SYSTEMS

RAID: What It Protects, What It Doesn't, and the URE Math

RAID levels are three ideas — stripe, mirror, parity — composed. The interesting parts are the failure math: why RAID 5 rebuilds fail at modern disk sizes, what the write hole is, and why RAID is not backup, mathematically.

PERFORMANCE

Branch Prediction: Why Sorted Data Runs Faster

The same loop over the same data runs 5x faster when the array is sorted. The instructions are identical. The difference is a gambler inside your CPU that's either winning or losing.

SYSTEMS

From Power Button to Kernel: How a PC Boots

At reset, an x86 CPU wakes up pretending it's 1978 — 16-bit mode, 1 MB address space. Everything after that is bootstrapping: firmware, boot sector or EFI application, protected mode, and finally a kernel. I wrote a bootloader to learn the path; here's the map.

PERFORMANCE

CPU Caches: The Memory Hierarchy Your Code Lives In

DRAM is ~100ns away; your CPU can do ~400 arithmetic operations in that time. Caches exist to hide that gap, and whether they succeed is decided by how your code lays out and walks its data.